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AVR Microcontroller Family Presentation Transcript
1.AVR Microcontroller Family
2.AVR
Atmel AVR 8-Bit Processors come in a variety of configurations and packages
They all share a common core – registers, instructions, basic I/O capabilities
Our focus is the ATMega16
Atmel AVR 8-Bit Processors come in a variety of configurations and packages
They all share a common core – registers, instructions, basic I/O capabilities
Our focus is the ATMega16
3.ATMega16 Features.
131 Instructions
32 8-bit GP registers
Throughput up to 16 MIPS
16K programmable flash (instructions)
512Bytes EEPROM
1K internal SRAM
Timers, serial and parallel I/O, ADC
131 Instructions
32 8-bit GP registers
Throughput up to 16 MIPS
16K programmable flash (instructions)
512Bytes EEPROM
1K internal SRAM
Timers, serial and parallel I/O, ADC
4.AVR CPU
PC: address of next instruction
IR: prefetched instruction
ID: current instruction
GPR: R0-R31
ALU
PC: address of next instruction
IR: prefetched instruction
ID: current instruction
GPR: R0-R31
ALU
5.AVR Memory
Flash: Machine instructions go here
SRAM: For runtime data
Note bus independence for data and instructions
EEPROM: Secondary storage
EEPROM and Flash memories have a limited lifetime of erase/write cycles
Flash: Machine instructions go here
SRAM: For runtime data
Note bus independence for data and instructions
EEPROM: Secondary storage
EEPROM and Flash memories have a limited lifetime of erase/write cycles
6.Flash Memory
Programs reside in word addressable flash storage
Word addresses range from 0000-1FFF (PC is 13 bits)
Byte addresses range 0000-3FFF (0x4000=16K)
Harvard Architecture
It is possible to use this storage area for constant data as well as instructions, violating the true spirit of this architecture
Instructions are 16 or 32-bits
Most are 16-bits and are executed in a single clock cycle
Programs reside in word addressable flash storage
Word addresses range from 0000-1FFF (PC is 13 bits)
Byte addresses range 0000-3FFF (0x4000=16K)
Harvard Architecture
It is possible to use this storage area for constant data as well as instructions, violating the true spirit of this architecture
Instructions are 16 or 32-bits
Most are 16-bits and are executed in a single clock cycle
7.SRAM
The ATMega16 has 1K (1024 bytes) of byte addressable static RAM
This is used for variable storage and stack space during execution
SRAM addresses start at $0060 and go through $045F
The reason for not starting at zero will be covered later
The ATMega16 has 1K (1024 bytes) of byte addressable static RAM
This is used for variable storage and stack space during execution
SRAM addresses start at $0060 and go through $045F
The reason for not starting at zero will be covered later
8.Clock
All processors are pushed through their fetch execute cycle by an alternating 0-1 signal, called a clock
The ATMega16 can use an internal or external clock signal
Clock signals are usually generated by an RC oscillator or a crystal
The internal clock is an RC oscillator programmable to 1, 2, 4, or 8 MHz
An external clock signal (crystal controlled) can be more precise for time critical applications
All processors are pushed through their fetch execute cycle by an alternating 0-1 signal, called a clock
The ATMega16 can use an internal or external clock signal
Clock signals are usually generated by an RC oscillator or a crystal
The internal clock is an RC oscillator programmable to 1, 2, 4, or 8 MHz
An external clock signal (crystal controlled) can be more precise for time critical applications
9.What does AVR RISC mean?
The acronym AVR has been reported to stand for: Advanced Virtual RISC and also for the chip's designers: Alf-Egil Bogen and Vegard Wollan who designed the basic architecture at the Norwegian Institute of Technology.
RISC stands for reduced instruction set computer.
CPU design with a reduced instruction set as well as a simpler set of instructions (like for example PIC and AVR)
The acronym AVR has been reported to stand for: Advanced Virtual RISC and also for the chip's designers: Alf-Egil Bogen and Vegard Wollan who designed the basic architecture at the Norwegian Institute of Technology.
RISC stands for reduced instruction set computer.
CPU design with a reduced instruction set as well as a simpler set of instructions (like for example PIC and AVR)
10.AVR Machine Language
AVR instructions are 16 or 32-bits
Each instruction contains an opcode
Opcodes generally are located in the initial bits of an instruction
Some instructions have operands encoded in the remaining bits
Opcode and operands are numbers, but their containers are simply some of the bits in the instruction
AVR instructions are 16 or 32-bits
Each instruction contains an opcode
Opcodes generally are located in the initial bits of an instruction
Some instructions have operands encoded in the remaining bits
Opcode and operands are numbers, but their containers are simply some of the bits in the instruction
11.Load Immediate
LDI Rd, K
Load a constant into a register (Rd = K)
1110 bbbb rrrr bbbb
Limitations: 16 <= d <= 31; 0x00 <= K <= 0xFF
Opcode is 1110
The register number is coded in bits 7-4
Only the last 4 bits of the register number are present; a leading 1 is assumed (1rrrr)
The constant is split into two nibbles
LDI Rd, K
Load a constant into a register (Rd = K)
1110 bbbb rrrr bbbb
Limitations: 16 <= d <= 31; 0x00 <= K <= 0xFF
Opcode is 1110
The register number is coded in bits 7-4
Only the last 4 bits of the register number are present; a leading 1 is assumed (1rrrr)
The constant is split into two nibbles
12.AVR 8-Bit RISC High Performance
True single cycle execution
? single-clock-cycle-per-instruction execution
One MIPS (mega instructions per second) per MHz
? up to 20 MHz clock
32 general purpose registers
? provide flexibility and performance when using high level languages
? prevents access to RAM
Harvard architecture
? separate bus for program and data memory
13.AVR 8-Bit RISC Low Power Consumption
1.8 to 5.5V operation
? will use all the energy stored in your batteries
A variety of sleep modes
? AVR Flash microcontrollers have up to six different sleep modes
? fast wake-up from sleep modes
Software controlled frequency
14.AVR 8-Bit RISC Compatibility
AVR® Flash microcontrollers share a single core architecture
? use the same code for all families
? 1 Kbytes to 256 Kbytes of code
?8 to 100 pins
? all devices have
Internal oscillators
15.AVR 8-Bit RISC – pico Power Technology
“Pico Power enables AVR to achieve the industry’s lowest power consumption with 650 nA with a RTC (real time clock) running and 100nA in Power Down sleep” (from ATMEL website)
- True 1.8V Supply Voltage - Minimized Leakage Current - Ultra Low Power 32 kHz Crystal Oscillator - Digital Input Disable Registers - Power Reduction Register
16.Manufacturers
Intel, Freescale, Microchip (PIC), TI, Zilog
Atmel AVR
Many Types, tinyAT, megaAT, automotive
Lighting, LCD
Share unified platform
Different #s of I/O control
Built-in Pull-up resistors
Ethernet, Serial Data, Auxiliary Power, USB
Analog I/O, Packaging, Interrupts, Math, JTAG
Get the right amount of memory for the job
17.Development Platforms
Everything Needed, All-In-One
Arduino / Diecimila
ATMega8 / ATMega168 based
Open source, multiplatform IDE
Cheap ($33 assembled!)?
Great Online Community
USB, power, protoshield available, breadboard, LEDs
Parallax (PIC)?
PICAXE (PIC)?
ArmExpress
Many Others
True single cycle execution
? single-clock-cycle-per-instruction execution
One MIPS (mega instructions per second) per MHz
? up to 20 MHz clock
32 general purpose registers
? provide flexibility and performance when using high level languages
? prevents access to RAM
Harvard architecture
? separate bus for program and data memory
13.AVR 8-Bit RISC Low Power Consumption
1.8 to 5.5V operation
? will use all the energy stored in your batteries
A variety of sleep modes
? AVR Flash microcontrollers have up to six different sleep modes
? fast wake-up from sleep modes
Software controlled frequency
14.AVR 8-Bit RISC Compatibility
AVR® Flash microcontrollers share a single core architecture
? use the same code for all families
? 1 Kbytes to 256 Kbytes of code
?8 to 100 pins
? all devices have
Internal oscillators
15.AVR 8-Bit RISC – pico Power Technology
“Pico Power enables AVR to achieve the industry’s lowest power consumption with 650 nA with a RTC (real time clock) running and 100nA in Power Down sleep” (from ATMEL website)
- True 1.8V Supply Voltage - Minimized Leakage Current - Ultra Low Power 32 kHz Crystal Oscillator - Digital Input Disable Registers - Power Reduction Register
16.Manufacturers
Intel, Freescale, Microchip (PIC), TI, Zilog
Atmel AVR
Many Types, tinyAT, megaAT, automotive
Lighting, LCD
Share unified platform
Different #s of I/O control
Built-in Pull-up resistors
Ethernet, Serial Data, Auxiliary Power, USB
Analog I/O, Packaging, Interrupts, Math, JTAG
Get the right amount of memory for the job
17.Development Platforms
Everything Needed, All-In-One
Arduino / Diecimila
ATMega8 / ATMega168 based
Open source, multiplatform IDE
Cheap ($33 assembled!)?
Great Online Community
USB, power, protoshield available, breadboard, LEDs
Parallax (PIC)?
PICAXE (PIC)?
ArmExpress
Many Others
18.LDI Examples
LDI R16, $2C
1110 0010 0000 1100 or 0xE20C
LDI R27, $0F27 is 11011
1110 0000 1011 1111 or 0xE0BF
Note that this instruction always
starts with E,
has the two nybbles of K at positions 2 and 0,
and encodes the register in nybble 1
LDI R16, $2C
1110 0010 0000 1100 or 0xE20C
LDI R27, $0F27 is 11011
1110 0000 1011 1111 or 0xE0BF
Note that this instruction always
starts with E,
has the two nybbles of K at positions 2 and 0,
and encodes the register in nybble 1
19.Add Registers
ADD Rd, Rr
Add the contents of two registers, store result in Rd (Rd = Rd + Rr)
0000 11rd dddd rrrr
Any registers: 0 <= r <= 31; 0 <= d <= 31
The opcode is 000011
The register numbers are coded in binary
Rr has its high bit split off from the others
ADD Rd, Rr
Add the contents of two registers, store result in Rd (Rd = Rd + Rr)
0000 11rd dddd rrrr
Any registers: 0 <= r <= 31; 0 <= d <= 31
The opcode is 000011
The register numbers are coded in binary
Rr has its high bit split off from the others
20.ADD Examples
ADD R16, R3
ddddd is 10000 and rrrrr is 00011
0000 1101 0000 0011 or 0x0D03
ADD R27, R17
ddddd is 11011, rrrrr is 10001
0000 1111 1011 0001 or 0x0FB1
Note that this instruction always
starts with 0,
followed by C, D, E, or F
and can have any values in the second byte
ADD R16, R3
ddddd is 10000 and rrrrr is 00011
0000 1101 0000 0011 or 0x0D03
ADD R27, R17
ddddd is 11011, rrrrr is 10001
0000 1111 1011 0001 or 0x0FB1
Note that this instruction always
starts with 0,
followed by C, D, E, or F
and can have any values in the second byte
21.Expanding Opcodes
22.A Machine Language Program
23.A Machine Language Program
24.AVR Studio
An integrated development environment
Provides a text editor
Supports the AVR assembler
Supports the gnu C compiler
Provides an AVR simulator and debugger
Provides programming support for the AVR processors via serial interface
An integrated development environment
Provides a text editor
Supports the AVR assembler
Supports the gnu C compiler
Provides an AVR simulator and debugger
Provides programming support for the AVR processors via serial interface
25.AVR Studio: New Project
Start AVR Studio
Click New Project
Select type: Assembler
Choose a project name
Select create options and pick a location
Start AVR Studio
Click New Project
Select type: Assembler
Choose a project name
Select create options and pick a location
26.AVR Studio: New Project
On the next dialog, select the Debug platform: AVR Simulator
Pick the device type: ATMega16
Finish
On the next dialog, select the Debug platform: AVR Simulator
Pick the device type: ATMega16
Finish
27.AVR Studio: Interface
Enter the program in the assembly source file that is opened for you.
Click the Assemble button (F7)
Enter the program in the assembly source file that is opened for you.
Click the Assemble button (F7)
28.AVR Studio: Assembler Report
29.AVR Studio: Debugger
30.
The first 2 instructions are completed
R16 and R17 have the expected values from the LDI instructions
The sum is placed in R16
$3B is the sum
The first 2 instructions are completed
R16 and R17 have the expected values from the LDI instructions
The sum is placed in R16
$3B is the sum
31.AVR Studio: Memory
Memory contents may be viewed (and edited) during debugging
You can view program (flash), data (SRAM), or EEPROM memory
You can also view the general purpose and I/O registers using this tool
Memory contents may be viewed (and edited) during debugging
You can view program (flash), data (SRAM), or EEPROM memory
You can also view the general purpose and I/O registers using this tool
32.Using Mnemonics
Rather than code the machine language program as a sequence of numeric word values expressed in hexadecimal, assembly language programmers usually use instruction mnemonics
Rather than code the machine language program as a sequence of numeric word values expressed in hexadecimal, assembly language programmers usually use instruction mnemonics
33.What's Next?
34.Relative Jump
35. Atmel AVR Usage:
AVRs have been used in various automotive applications such as security, safety, powertrain and entertainment systems. Atmel has recently launched a new publication "Atmel Automotive Compilation" to help developers with automotive applications. Some current usages are in BMW, Daimler-Chrysler and TRW.
AVRs have been used in various automotive applications such as security, safety, powertrain and entertainment systems. Atmel has recently launched a new publication "Atmel Automotive Compilation" to help developers with automotive applications. Some current usages are in BMW, Daimler-Chrysler and TRW.
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